1. Field of the Invention
The present invention relates to data communications. In particular, the present invention relates to routers and the detection and communication of missing Phy Level logic to a host processor.
2. The Prior Art
Background
The Personal Computer Interface (PCI) bus standard has found widespread use in today's data communications system, primarily because of the advantages found in the PCI standard. For example, one advantage of the PCI design is that up to 256 devices can be attached to one PCI local bus, and up to 256 PCI busses can exist in one system. Furthermore, PCI is a Plug and Play architecture—it is auto-configured by system BIOS. This means that system resource assignments destined for expansion devices (such as IRQ assignments and address space) is all automated, there is a greatly reduced chance of resource allocation conflicts. These features of the PCI bus make it one of the most suitable architectures available to the PC industry today.
As is known by those skilled in the art, the basic components of the PCI bus include: the PCI BIOS, a CPU, a CPU Cache, System Cache, System Memory, a PCI Bridge, and a Peripheral bus. Each component performs a specific task associated with accomplishing communication via the PCI bus. Thus, each component has a specific method that it uses to interact with adjacent components. Because these methods of component interaction are the same in all PCI systems, the PCI design is inherently adaptable to a variety of configurations. It is standard to include embedded devices and peripheral devices on the same bus for this reason.
One application where a PCI system must adapt for a variety of configurations is within a router. FIG. 1 shows a prior art diagram of a router having a PCI-compliant bus deployed therein.
FIG. 1 includes a router motherboard 100, known as a front card. Front card 100 has hardware and software standard in the art. FIG. 1 also includes a daughterboard 101, known as a back card. Back card 101 represents a Fast Ethernet-compliant (FE) device coupled to front card 100. Back card 101 includes a FE Media Access Controller (MAC) 110 configured to perform OSI-standard Layer 2 functions. Back card 101 also includes a FE Physical (Phy) controller 112 configured to perform OSI-standard Layer 1 functions. FE Phy 112 is coupled to FE MAC 110 via a MII (Media Independent Interface) interface 114 standard in the art.
Back card 101 also includes an identification programmable read-only memory (ID PROM) 104 configured to provide information about the back card 101 to the front card 100 via a serial bus 102 standard in the art.
As can be seen by inspection of FIG. 1, in order to couple back card 101 to the front card 100, the FE MAC 110 must be coupled to the front card 100 via a 32-bit wide PCI address data bus (PCI_AD) 108. Additionally, the PCI identification select connection (PCI_Idsel) 106, with resistor 105 serially disposed therein, and serial bus 102 must also be coupled. Thus, a suitable physical connector capable of making this plethora of connections must be provided.
As will be appreciated by those skilled in the art, such a connector is rather large when compared to the size of the components being connected, especially given the ever-decreasing size of semiconductor devices. Because circuit board real estate is so valuable, the prior art searched for ways to eliminate the area penalty imposed by a connector which must make so many connections.
FIG. 2 shows one solution proposed by the prior art. Similar designations are intended to designate substantially similar matter herein throughout. As can be seen by inspection of FIG. 2, the solution proposed was to locate the FE MAC 110 on the front card 100, thus eliminating the need to physically couple the PCI_AD bus 108 through a physical connector and re-gaining the area savings by eliminating the need for a large connector.
However, the prior art solution of FIG. 2 posed certain problems.
By way of background, when a PCI-compliant device is coupled to a host device, certain procedures occur to ensure a proper connection. An important aspect of the PCI standard is the identification of devices which have made themselves available to the bus. When a device is present, it makes its presence known by responding to the host when its ISDEL input is driven high during a config cycle. During the config cycle, a device is targeted by a combination of Command/byte enable signals (C/BE[3:1]=101) during the PCI address phase, and by making active the devices' IDSEL input. All devices on the PCI bus will look at their IDSEL inputs and will respond if the IDSEL input is active. Typically the IDSEL pins are driven by one of the Address bus bits AD[31:11] which is typically resistively coupled using a 50K Ohm resistor 105. Each device gets its own Address bit.
For example:                PCI_AD[11]->FE MAC #1 IDSEL input        PCI_AD[12]->FE MAC #2 IDSEL input        
As can be seen by inspection of FIG. 1, this procedure worked fine (i.e. host software could easily identify a missing Fast Ethernet interface) when the FE MAC 110 was located on the back card 101. However, when the FE MAC 110 was moved to the front card 100, the FE MAC 110 was now permanently coupled to the front card 100 through the connection of the PCI AD signal to the FE MAC's IDSEL 106. Thus, the FE MAC IDSEL connection will always be driven when the host checks for devices, creating the risk that the FE MAC may mistakenly believe that a device is connected when in fact there is no FE Phy present.
To compensate, the prior art developed software to detect whether an FE Phy was present. One example of such software utilized the ID PROM to determine whether a FE Phy was present. In this example, the ID PROM was programmed to communicate whether there was a FE Phy installed on a given channel.
However, such solutions have certain disadvantages. If the ID PROM is not programmed correctly or malfunctions, the front card 100 may mistakenly sense that a back card device is connected when in fact no FE Phy is present In this case, the PCI scan of the FE MAC device would identify the interface as being present.
Furthermore, such software adds processing overhead and may be prone to errors, thereby decreasing the overall efficiency of the host device.
Hence there is a need for a method and apparatus to identify when a FE Phy is present in a PCI-compliant system which does not suffer from the disadvantages of the prior art.